Avago Technologies LSI53C895A User Manual
Page 186
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Registers
When performing consecutive 8-bit reads of the
,
SCSI Interrupt Status Zero (SIST0)
, and
registers (in any order), insert a delay equivalent to 12 CLK
periods between the reads to ensure the interrupts clear properly. Also,
if reading the registers when both the
Interrupt Status Zero (ISTAT0)
SIP
and DIP bits may not be set, read the SIST0 and SIST1 registers before
the DSTAT register to avoid missing a SCSI interrupt. For more
information on interrupts, refer to
Chapter 2, “Functional Description.”
M/A
Initiator Mode: Phase Mismatch; Target Mode:
SATN/ Active
7
In the initiator mode, this bit is set if the SCSI phase
asserted by the target does not match the instruction.
The phase is sampled when SREQ/ is asserted by the
target. In target mode, this bit is set when the SATN/
signal is asserted by the initiator.
CMP
Function Complete
6
This bit is set when an arbitration only or full arbitration
sequence is completed.
SEL
Selected
5
This bit is set when the LSI53C895A is selected by
another SCSI device. The Enable Response to Selection
bit must be set in the
register (and
the
and
register must hold the chip’s ID) for the
LSI53C895A to respond to selection attempts.
RSL
Reselected
4
This bit is set when the LSI53C895A is reselected by
another SCSI device. The Enable Response to
Reselection bit must be set in the SCID register (and the
and
registers must hold the chip’s ID) for the
LSI53C895A to respond to reselection attempts.
SGE
SCSI Gross Error
3
This bit is set when the LSI53C895A encounters a SCSI
Gross Error Condition. The following conditions can result
in a SCSI Gross Error Condition:
•
Data Underflow – reading the SCSI FIFO when no
data is present.