Avago Technologies LSI53C895A - Manual (Page 356)

IX-10 Index
start (Cont.)
SCSI transfer (SST) 4-26
sequence (START) 4-22
static block move selector (SBMS) 4-106
STEST2 register 2-26
STOP command 2-9
stop signal 3-7
STOP/ signal 3-7
store 2-24
stress ratings 6-2
subsystem ID 2-58
subsystem ID (SID) 4-11
subsystem ID access (SIDA) 4-18
subsystem vendor ID 2-58
subsystem vendor ID (SVID) 4-10
SVID 2-58
SWIDE register 2-53 , 2-54
SXFER 2-42
SYNC_IRQD (SI) 4-52
synchronous
data transfer rates 2-40
operation 2-40
SCSI receive 2-33
SCSI send 2-32
synchronous clock conversion factor (SCF[2:0]) 4-30
system signals 3-4
T
table indirect 5-19
mode 5-17
table relative 5-19
target
mode 5-8 , 5-14
SATN/ active (M/A) 4-78
mode (TRG) 4-23
ready 3-6
timing 6-15
TCK 3-16
TDI 3-16
TDO 3-16
TEMP register 5-35
temporary (TEMP) 4-58
termination 2-38
test interface signals 3-16
TEST_HSC 3-16
TEST_RST/ 3-16
third dword 5-35
timer test mode (TTM) 4-94
TMS 3-16
TolerANT 1-5 , 6-8
enable (TE) 4-93
technology 1-5
benefits 1-5
electrical characteristics 6-8
totem pole output 3-3
transfer
control 2-24
control instructions 5-26
and SCRIPTS instruction prefetching 2-24
count 5-33
counter 5-12
information 2-19
rate
synchronous 2-40
TRDY/ 2-9 , 3-6
TRST/ 3-16
U
Ultra SCSI
clock conversion factor bits 4-31
enable (USE) 4-29
high voltage differential transfers 20.0 mbytes (8-bit
transfers) or 40.0 mbytes (16-bit transfers) 80 MHz clock
6-62
single-ended transfers 20.0 mbytes (8-bit transfers) or 40.0
mbytes (16-bit transfers) quadrupled 40 MHz clock 6-61
Ultra2 SCSI 1-4
benefits 1-4
designing an Ultra2 SCSI system 2-22
LVDlink 2-34
synchronous data transfers 2-42
transfers 40.0 mbytes (8-bit transfers) or 80.0 mbytes
(16-bit transfers) quadrupled 40 MHz clock 6-63
unexpected disconnect (UDC) 4-75 , 4-79
updated address (UA) 4-110
upper register address line (A7) 5-23
use data8/SFBR 5-22
V
VDD 3-17
-A 3-17
-core 3-17
vendor
ID (VID) 4-3
unique enhancement, bit 1 (VUE1) 4-28
unique enhancements, bit 0 (VUE0) 4-28
version (VER[2:0]) 4-16
VSS 3-17
-A 3-17
-core 3-17
W
wait
disconnect instruction 5-16
for a disconnect 2-19
for valid phase 5-31
reselect instruction 5-17
select instruction 5-14
wide SCSI
chained block moves 2-51
receive (WSR) 4-29
receive bit 2-53
send (WSS) 4-28
send bit 2-52
won arbitration (WOA) 4-44
write
read instructions 5-22
read system memory from SCRIPTS 5-34
write and invalidate
enable (WIE) 4-4
enable (WRIE) 4-58
WSR bit 2-53
WSS flag 2-53