Avago Technologies LSI53C895A - Manual (Page 69)

SCSI Functional Description 2-43
2.2.16 Interrupt Handling
The SCRIPTS processors in the LSI53C895A perform most functions
independently of the host microprocessor. However, certain interrupt
situations must be handled by the external microprocessor. This section
explains all aspects of interrupts as they apply to the LSI53C895A.
2.2.16.1 Polling and Hardware Interrupts
The external microprocessor is informed of an interrupt condition by
polling or hardware interrupts. Polling means that the microprocessor
must continually loop and read a register until it detects a bit that is set
indicating an interrupt. This method is the fastest, but it wastes CPU time
that could be used for other system tasks. The preferred method of
detecting interrupts in most systems is hardware interrupts. In this case,
the LSI53C895A asserts the Interrupt Request (IRQ/) line that interrupts
the microprocessor, causing the microprocessor to execute an interrupt
service routine. A hybrid approach would use hardware interrupts for
long waits, and use polling for short waits.
2.2.16.2 Registers
The registers in the LSI53C895A that are used for detecting or defining
interrupts are
Interrupt Status Zero (ISTAT0) , Interrupt Status One
(ISTAT1) , Mailbox Zero (MBOX0) , Mailbox One (MBOX1) , SCSI Interrupt
Status Zero (SIST0) , SCSI Interrupt Status One (SIST1) , DMA Status
(DSTAT) , SCSI Interrupt Enable Zero (SIEN0) , SCSI Interrupt Enable
One (SIEN1) , DMA Control (DCNTL) , and DMA Interrupt Enable (DIEN) .
ISTAT – The ISTAT register includes the Interrupt Status Zero (ISTAT0) ,
Interrupt Status One (ISTAT1) , Chip Test Zero (CTEST0) , and Mailbox
One (MBOX1) registers. It is the only register that can be accessed as a
slave during the SCRIPTS operation. Therefore, it is the register that is
polled when polled interrupts are used. It is also the first register that
should be read after the IRQ/ pin is asserted in association with a
hardware interrupt. The INTF (Interrupt-on-the-Fly) bit should be the first
interrupt serviced. It must be written to one to be cleared. This interrupt
must be cleared before servicing any other interrupts.
See Register 0x14, Interrupt Status Zero (ISTAT0) register, Bit 5 Signal
process in Chapter 4, “Registers,” for additional information.