Avago Technologies LSI53C895A - Manual (Page 94)

3-6 Signal Descriptions
3.3.3 Interface Control Signals
Table 3.4 describes the Interface Control signals.
PAR 30 Y12 T/S 8 mA PCI Parity is the even parity bit
that protects the AD[31:0]
and C_BE[3:0]/ lines. During
the address phase, both the
address and command bits
are covered. During data
phase, both data and byte
enables are covered.
Table 3.3 Address and Data Signals (Cont.)
Name PQFP BGA Pos Type Strength Description
Table 3.4 Interface Control Signals
Name PQFP BGA Pos Type Strength Description
FRAME/ 21 V9 S/T/S 8 mA PCI Cycle Frame is driven by the
current master to indicate the
beginning and duration of an
access. FRAME/ is asserted to
indicate that a bus transaction is
beginning. While FRAME/ is
deasserted, either the transaction is
in the final data phase or the bus is
idle.
TRDY/ 24 W10 S/T/S 8 mA PCI Target Ready indicates the target
agent’s (selected device’s) ability to
complete the current data phase of
the transaction. TRDY/ is used with
IRDY/. A data phase is completed
on any clock when used with IRDY/.
A data phase is completed on any
clock when both TRDY/ and IRDY/
are sampled asserted. During a
read, TRDY/ indicates that valid data
is present on AD[31:0]. During a
write, it indicates that the target is
prepared to accept data. Wait cycles
are inserted until both IRDY/ and
TRDY/ are asserted together.