Avago Technologies LSI53C895A - Manual (Page 116)

4-8 Registers
whether to use Read, Read Line, or Read Multiple
commands for performing read cycles as a bus master.
Devices participating in the caching protocol use this field
to know when to retry burst accesses at cache line
boundaries. These devices can ignore the PCI cache
support lines (SDONE and SB0/) when this register is
cleared to 0. If this register is programmed to a number
which is not a power of 2, the device will not use PCI
performance commands to perform data transfers.
Register: 0x0D
Latency Timer
Read/Write
LT Latency Timer [7:0]
The Latency Timer register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. The LSI53C895A supports this timer. All eight
bits are writable, allowing latency values of 0–255 PCI
clocks. Use the following equation to calculate an
optimum latency value for the LSI53C895A.
Latency = 2 + (Burst Size x (typical wait states + 1))
Values greater than optimum are also acceptable.
Register: 0x0E
Header Type
Read Only
HT Header Type [7:0]
This register identifies the layout of bytes 0x10 through
0x3F in configuration space and also whether or not the
device contains multiple functions. Since the LSI53C895A
is not a multifunction controller the value of this register
is 0x00.
7 0
LT
0 0 0 0 0 0 0 0
7 0
HT
0 0 0 0 0 0 0 0