4 masking, Section 2.2.16.4, “masking – Avago Technologies LSI53C895A User Manual
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Functional Description
chip’s behavior when the SATN/ interrupt is enabled during Target mode
operation. The Interrupt-on-the-Fly interrupt is also nonfatal, since
SCRIPTS can continue when it occurs.
The reason for nonfatal interrupts is to prevent the SCRIPTS from
stopping when an interrupt occurs that does not require service from the
CPU. This prevents an interrupt when arbitration is complete (CMP set),
when the LSI53C895A is selected or reselected (SEL or RSL set), when
the initiator asserts ATN (target mode: SATN/ active), or when the
General Purpose or Handshake-to-Handshake timers expire. These
interrupts are not needed for events that occur during high-level
SCRIPTS operation.
2.2.16.4 Masking
Masking an interrupt means disabling or ignoring that interrupt. Interrupts
can be masked by clearing bits in the
and
SCSI Interrupt Enable One (SIEN1)
(for SCSI interrupts)
registers or
(for DMA interrupts) register.
How the chip responds to masked interrupts depends on: whether polling
or hardware interrupts are being used; whether the interrupt is fatal or
nonfatal; and whether the chip is operating in the Initiator or Target mode.
If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS
do not stop, the appropriate bit in the
SCSI Interrupt Status Zero (SIST0)
or
SCSI Interrupt Status One (SIST1)
is still set, the SIP bit in the
Interrupt Status Zero (ISTAT0)
is not set, and the IRQ/ pin is not
asserted.
If a fatal interrupt is masked and that condition occurs, then the SCRIPTS
still stop, the appropriate bit in the
,
, or
SCSI Interrupt Status One (SIST1)
register is
set, and the SIP or DIP bit in the
Interrupt Status Zero (ISTAT0)
register
is set, but the IRQ/ pin is not asserted.
Interrupts can be disabled by setting SYNC_IRQD bit 0 in the
register. If an interrupt is already asserted and
SYNC_IRQD is then set, the interrupt will remain asserted until serviced.
At this point, the IRQ/ pin is blocked for future interrupts until this bit is
cleared. When the LSI53C895A is initialized, enable all fatal interrupts if
you are using hardware interrupts. If a fatal interrupt is disabled and that