Avago Technologies LSI53C895A - Manual (Page 292)

6-32 Electrical Specifications
Table 6.29 Burst Read, 64-Bit Address and Data
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid 2 11 ns
t
10
CLK HIGH to GPIO1_MASTER/ HIGH – 20 ns