Avago Technologies LSI53C895A - Manual (Page 277)

PCI and External Memory Interface Timing Diagrams 6-17
Figure 6.12 PCI Configuration Register Write
Table 6.19 PCI Configuration Register Write
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid – 11 ns
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD
(Driven by Master)
C_BE/
(Driven by Master)
PAR
(Driven by Master)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C895A)
STOP/
(Driven by LSI53C895A)
DEVSEL/
(Driven by LSI53C895A)
IDSEL
(Driven by Master)
t
1
t
2
t
3
Data In
Byte Enable
Addr
In
CMD
t
1
t
2 t
2
t
2
t
2
t
3
t
1
t
1
t
1
t
2
t
2
t
1
t
2
t
1