Avago Technologies LSI53C895A - Manual (Page 12)

xii Contents
6.37 Target Asynchronous Send 6-58
6.38 Target Asynchronous Receive 6-59
6.39 Initiator and Target Synchronous Transfer 6-63
6.40 LSI53C895A 272-Pin BGA Top View 6-65
6.41 LSI53C895A 208-Pin Plastic Quad Flat Pack 6-68
6.42 LSI53C895A 208 PQFP Mechanical Drawing
(Sheet 1 of 2)
6-74
6.43 LSI53C895A 272 PBGA Mechanical Drawing 6-76
B.1 16 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte
Interface with 150 ns Memory
B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4
Tables
2.1 PCI Bus Commands and Encoding Types for the
LSI53C895A
2-4
2.2 PCI Cache Mode Alignment 2-13
2.3 Bits Used for Parity Control and Generation 2-27
2.4 SCSI Parity Control 2-28
2.5 SCSI Parity Errors and Interrupts 2-28
2.6 HVD Signals 2-35
2.7 Parallel ROM Support 2-56
2.8 Mode A Serial EEPROM Data Format 2-58
2.9 Power States 2-61
3.1 LSI53C895A Internal Pull-ups 3-3
3.2 System Signals 3-4
3.3 Address and Data Signals 3-5
3.4 Interface Control Signals 3-6
3.5 Arbitration Signals 3-8
3.6 Error Reporting Signals 3-8
3.7 Interrupt Signals 3-9
3.8 SCSI GPIO Signals 3-10
3.9 SCSI Bus Interface Signal 3-11
3.10 SCSI Signals 3-12
3.11 SCSI Control Signals 3-13
3.12 Flash ROM and Memory Interface Signals 3-14
3.13 Test Interface Signals 3-16