Avago Technologies LSI53C895A - Manual (Page 351)

Index IX-5
disable (Cont.)
halt on parity error or ATN (target only) (DHP) 4-24
internal load and store (DILS) 4-99
single initiator response (DSI) 4-94
disconnect 2-19
disconnect instruction 5-14
DMA
byte counter (DBC) 4-64
command (DCMD) 4-65
control (DCNTL) 4-71
direction (DDIR) 4-62
FIFO 2-8 , 2-29 , 2-44
(DF) 4-63
(DFIFO) 4-58
byte offset counter, bits [9:8] (BO[9:8]) 4-63
empty (DFE) 4-40
size (DFS) 4-62
interrupt 2-45 , 2-46 , 2-48
enable (DIEN) 4-70
pending (DIP) 4-51
mode (DMODE) 4-67
SCRIPTS
pointer (DSP) 4-65
pointer save (DSPS) 4-66
status (DSTAT) 4-40
DMA next
address (DNAD) 4-65
address 64 (DNAD64) 4-107
DMODE 2-6
register 2-24
DSA
relative 5-36
relative selector (DRS) 4-106
DSPS register 5-34
DSTAT 2-44 , 2-48 , 2-49
dual address cycles
command 2-7
dynamic block move selector (DBMS) 4-107
E
enable
64-bit
direct BMOV (EN64DBMV) 4-101
table indirect BMOV (EN64TIBMV) 4-101
bus mastering (EBM) 4-4
I/O space (EIS) 4-5
jump on nondata phase mismatches (ENNDJ) 4-99
memory space (EMS) 4-4
parity
checking 2-26
checking (EPC) 4-23
error response (EPER) 4-4
phase mismatch jump (ENPMJ) 4-98
read
line (ERL) 4-69
multiple (ERMP) 4-69
response to
reselection (RRE) 4-31
selection (SRE) 4-31
wide SCSI (EWS) 4-30
enabling cache mode 2-10
encoded
chip SCSI ID (ENC) 4-31
destination SCSI ID
(ENC) 4-36
(ENID) 4-39
SCSI destination ID 5-20
entry storage address (ESA) 4-111
error reporting signals 3-8
even parity 2-26
expansion ROM base
address (ERBA) 4-12
address register 2-56
extend SREQ/SACK filtering (EXT) 4-92
external
clock 6-12
memory interface 2-56
external memory interface
configuration 2-56
multiple byte accesses 6-14
slow memory 2-56
extra clock cycle of data setup (EXC) 4-24
F
fetch
enable (FE) 4-84
pin mode (FM) 4-57
FIFO
byte control (FBL[2:0]) 4-61
byte control (FBL3) 4-60
flags (FF[3:0]) 4-44
flags, bit 4 (FF4) 4-47
first dword 5-5 , 5-13 , 5-22 , 5-26 , 5-36
flush DMA FIFO (FLF) 4-57
flushing (FLSH) 4-52
FRAME/ 3-6
frequency lock (LOCK) 4-97
full arbitration, selection/reselection 4-22
function complete 2-45
(CMP) 4-75 , 4-78
G
general purpose
(GPREG0) 4-36
I/O (GPIO) 4-36
I/O pin 0 3-10
I/O pin 1 3-10
I/O pin 2 3-10
I/O pin 3 3-10
I/O pin 4 3-10
I/O pin 5 3-10
I/O pin 6 3-10
I/O pin 7 3-10
I/O pin 8 3-10
pin control zero (GPCNTL0) 4-84
timer expired (GEN) 4-77 , 4-80
timer period (GEN[3:0]) 4-87
timer scale factor (GENSF) 4-87
general purpose I/O (GPIO[8:5]) 4-102
general purpose one (GPREG1) 4-102
GNT/ 3-8
GPIO enable (GPIOEN[8:5]) 4-102
GPIO enable, bits [1:0] (GPIO[1:0]) 4-85
GPIO enable, bits [4:2] (GPIO[4:2]) 4-84
GPIO0_ FETCH/ 3-10
GPIO1_ MASTER/ 3-10
GPIO2 3-10
GPIO3 3-10
GPIO4 3-10