Avago Technologies LSI53C895A - Manual (Page 287)

PCI and External Memory Interface Timing Diagrams 6-27
Figure 6.19 Back to Back Read, 32-Bit Address and Data
CLK
(Driven by System)
FRAME/
(Driven by LSI53C895A)
AD
(Driven by LSI53C895A-
C_BE/
(Driven by LSI53C895A)
PAR
(Driven by LSI53C895A-
IRDY/
(Driven by LSI53C895A)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
Addr; Target-Data )
Addr; Target-Data)
GNT/
(Driven by Arbiter)
REQ/
(Driven by LSI53C895A)
GPIO1_MASTER/
(Driven by LSI53C895A)
GPIO0_FETCH/
(Driven by LSI53C895A )
Out
CMD BE
Addr
Out
t
9
Data In
In Out
BE CMD
Addr
Out
t
6
t
5
t
3
t
4
t
3
t
3
t
3
t
3
t
1
t
2
t
2
t
1
t
2
t
1
t
2
t
10
t
1
Data In
In