Avago Technologies LSI53C895A - Manual (Page 103)

Flash ROM and Memory Interface Signals 3-15
MAS1/ 185 M1 O 4 mA Memory Address Strobe 1. This
pin is used to latch in the most
significant address byte (bits [15:8])
of an external EEPROM or flash
memory. Since the LSI53C895A
moves addresses eight bits at a
time, this pin connects to the clock
of an external bank of flip-flops
which assemble up to a 20-bit
address for the external memory.
MAD[7:0] 69, 70, 71,
72, 74, 75,
76, 77 N19, N20,
M18, M19,
M20, L19,
L20, K20 I/O 4 mA Memory Address/Data Bus. This
bus is used in conjunction with the
memory address strobe pins and
external address latches to
assemble up to a 20-bit address for
an external EEPROM or flash
memory. This bus will put out the
least significant byte first and
finishes with the most significant
bits. It is also used to write data to
a flash memory or read data into the
chip from external EEPROM/flash
memory. These pins have static
pull-downs.
Table 3.12 Flash ROM and Memory Interface Signals (Cont.)
Name PQFP BGA Pos Type Strength Description