Avago Technologies LSI53C895A - Manual (Page 20)

1-4 General Description
Additional features of the LSI53C895A include:
•
Hardware control of SCSI activity LED.
•
Nine GPIO Pins.
•
32-bit ISTAT registers ( Interrupt Status Zero (ISTAT0) , Interrupt
Status One (ISTAT1) , Mailbox Zero (MBOX0) , and Mailbox One
(MBOX1) ).
•
Optional 944 byte DMA FIFO supports large block transfers at Ultra2
SCSI speeds. The default FIFO size of 112 bytes is also supported.
1.2 Benefits of Ultra2 SCSI
Ultra2 SCSI is an extension of the SPI-2 draft standard that allows faster
synchronous SCSI transfer rates. It also defines a new physical layer,
LVD SCSI, that provides an incremental evolution from SCSI-2 and Ultra
SCSI. When enabled, Ultra2 SCSI performs 40 megatransfers per
second, resulting in approximately twice the synchronous transfer rates
of Ultra SCSI. The LSI53C895A can perform 16-bit, Ultra2 SCSI
synchronous transfers as fast as 80 Mbytes/s. This advantage is most
noticeable in heavily loaded systems or with applications with large block
requirements, such as video on-demand and image processing.
An advantage of Ultra2 SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The primary software changes required enable the chip to perform
synchronous negotiations for Ultra2 SCSI rates and to enable the clock
quadrupler. Ultra2 SCSI uses the same connectors as Ultra SCSI, but
can operate with longer cables and more devices on the bus.
Chapter 2, “Functional Description,” contains more information on
migrating an Ultra SCSI design to support Ultra2 SCSI.
1.3 Benefits of LVDlink
The LSI53C895A supports LVD for SCSI. This signaling technology
increases the reliability of SCSI data transfers over longer distances than
are supported by SE SCSI. The low current output of LVD allows the I/O
transceivers to be integrated directly onto the chip. LVD provides the
reliability of HVD SCSI without the added cost of external differential