Avago Technologies LSI53C895A - Manual (Page 127)

SCSI Registers 4-19
additional information about using this register refer to the
Section 2.5, “Alternative SSVID/SSID Loading
Mechanism,”
topic in Chapter 2 .
4.2 SCSI Registers
The control registers for the SCSI core are directly accessible from the
PCI bus using Memory or I/O mapping. The address map of the SCSI
registers is shown in
Table 4.2 .
Note: The only registers that the host CPU can access while the
LSI53C895A is executing SCRIPTS are the
Interrupt Status
Zero (ISTAT0) , Interrupt Status One (ISTAT1) and
Mailbox Zero (MBOX0) , Mailbox One (MBOX1) registers;
attempts to access other registers interfere with the
operation of the chip. However, all operating registers are
accessible with SCRIPTS. All read data is synchronized
and stable when presented to the PCI bus.