Altera PCI Compiler - Manual (Page 9)

Altera Corporation User Guide Version 11.1 ix
PCI Compiler
Contents
System Options-2 ................................................................................................................................... 6–9
PCI Bus Speed .............................................................................................................................. 6–9
PCI Data Bus Width .................................................................................................................... 6–9
PCI Clock/Reset Settings ........................................................................................................... 6–9
PCI Bus Arbiter ......................................................................................................................... 6–10
PCI Configuration ............................................................................................................................... 6–11
PCI Base Address Registers ..................................................................................................... 6–11
PCI Read-Only Registers ......................................................................................................... 6–11
Setting the PCI Base Address Register Values ..................................................................... 6–11
Manual Setting of the BAR Size & Avalon Base Address ................................................... 6–14
Avalon Configuration ......................................................................................................................... 6–16
Chapter 7. Functional Description
Functional Overview ............................................................................................................................. 7–1
PCI-Avalon Bridge Blocks ............................................................................................................... 7–2
Avalon-MM Ports ....................................................................................................................... 7–3
Control/Status Register Module .............................................................................................. 7–5
PCI MegaCore Function ............................................................................................................. 7–5
PCI Bus Arbiter ........................................................................................................................... 7–6
Other PCI-Avalon Bridge Modules .......................................................................................... 7–6
PCI Operational Modes ................................................................................................................... 7–6
PCI Target-Only Peripheral Mode Operation ........................................................................ 7–6
PCI Master/Target Peripheral Mode Operation .................................................................... 7–8
PCI Host-Bridge Device Mode Operation ............................................................................. 7–10
Performance Profiles ...................................................................................................................... 7–11
Target Performance .................................................................................................................. 7–12
Master Performance .................................................................................................................. 7–12
Interface Signals ................................................................................................................................... 7–13
PCI Bus Arbiter Signals ................................................................................................................. 7–14
PCI Bus Commands ............................................................................................................................ 7–15
PCI Target Operation .......................................................................................................................... 7–15
Non-Prefetchable Operations ....................................................................................................... 7–17
Non-Prefetchable Write Operations ....................................................................................... 7–18
I/O Write Operations ............................................................................................................... 7–19
Non-Prefetchable Read Operations ........................................................................................ 7–19
Prefetchable Operations ................................................................................................................ 7–21
Prefetchable Write Operations ................................................................................................ 7–22
Prefetchable Read Operations ................................................................................................. 7–23
PCI-to-Avalon Address Translation ............................................................................................ 7–26
PCI Master Operation ......................................................................................................................... 7–27
Avalon-To-PCI Read & Write Operation .................................................................................... 7–28
Avalon-to-PCI Write Requests ................................................................................................ 7–31
Avalon-to-PCI Read Requests ................................................................................................. 7–32
Arbitration Among Pending PCI Master Requests .............................................................. 7–34
Avalon-to-PCI Address Translation ............................................................................................ 7–35
Ordering of Requests ..................................................................................................................... 7–38
Ordering of Avalon-to-PCI Operations ................................................................................. 7–39