Altera PCI Compiler - Manual (Page 332)

8–2 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Features
Figure 8–1. Altera PCI Testbench Block Diagram
To use the PCI testbench, be sure you have a basic understanding of PCI
bus architecture and operations.This document describes the features
and applications of the PCI testbench to help you successfully design and
verify your design.
Features The PCI testbench includes the following features:
■ Easy to use simulation environment for any standard VHDL or
Verilog HDL simulator
■ Open source VHDL and Verilog HDL files
■ Flexible PCI bus functional model to verify your application that
uses any Altera PCI MegaCore function
■ Simulates all basic PCI transactions including memory read/write
operations, I/O read/write transactions, and configuration
read/write transactions
■ Simulates all abnormal PCI transaction terminations including target
retry, target disconnect, target abort, and master abort
■ Simulates PCI bus parking
Bus
Monitor
Arbiter
Pull Ups
PCI Bus
Altera PCI Testbench
Master
Transactor
Target
Transactor
Testbench Modules
Altera
PCI
Compiler
System Generated
Using SOPC Builder
Altera Device
On-chip
Memory
DMA
Engine
System
Interconnect
Fabric