Altera PCI Compiler - Manual (Page 171)

Altera Corporation User Guide Version 11.1 3–97
October 2011
Functional Description
7
The function asserts irdyn to inform the target that the function is ready to receive data. On the first
data phase the function asserts irdyn regardless of whether the lm_rdyn signal is asserted on
the local side to indicate that the local side is ready to accept data. For subsequent data phases, the
function does not assert
irdyn unless the local side is ready to accept data.
The target claims the transaction by asserting devseln . In this case, the target performs a fast
address decode. The target also asserts ack64n to inform the function that it can transfer 64-bit
data.
During this clock cycle, the function also asserts lm_tsr[3] to inform the local side that it is in data
phase mode.
8
The target asserts trdyn to inform the function that it is ready to transfer data. Because the function
has already asserted irdyn , a data phase is completed on the rising edge of clock cycle 9.
At the same time, lm_tsr[9] is asserted to indicate to the local side that the target can transfer
64-bit data.
9 The function asserts lm_ackn to inform the local side that the function has registered data from the
PCI side on the previous cycle and is ready to send the data to the local side master interface.
Because
lm_rdyn was asserted in the previous cycle and lm_ackn is asserted in the current
cycle, the function asserts lm_dxfrn . The assertion of the lm_dxfrn , l_ldat_ackn , and
l_hdat_ackn signals indicate to the local side that valid data is available on the l_dato bus.
Because
irdyn and trdyn are asserted, another data phase is completed on the PCI side on the
rising edge of clock cycle 10.
On the local side, the lm_lastn signal is asserted. Because lm_lastn , irdyn , and trdyn are
asserted during this clock cycle, this action guarantees to the local side that, at most, two more data
phases will occur on the PCI side: one during this clock cycle and another on the following clock cycle
(clock cycle 10). The last data phase on the PCI side takes place during clock cycle 10.
The function also asserts lm_tsr [8] in the same clock cycle to inform the local side that a
successful data transfer has occurred on the PCI bus during the previous clock cycle.
Table 3–38. Zero-Wait State Burst Memory Read Master Transaction (Part 2 of 3)
Clock
Cycle
Event