Altera PCI Compiler - Manual (Page 87)

Altera Corporation User Guide Version 11.1 3–13
October 2011
Functional Description
req64n (1) STS Low Request 64-bit transfer. The req64n signal is an output from
the current bus master and indicates that the master is
requesting a 64-bit transaction.
req64n has the same timing
as framen . This signal is not implemented in pci_mt32 and
pci_t32 .
irdyn (1) STS Low Initiator ready. The irdyn signal is an output from a bus master
to its target and indicates that the bus master can complete the
current data transaction. In a write transaction,
irdyn
indicates that the address bus has valid data. In a read
transaction,
irdyn indicates that the master is ready to accept
data.
devseln (1) STS Low Device select. Target asserts devseln to indicate that the
target has decoded its own address and accepts the
transaction.
ack64n (1) STS Low Acknowledge 64-bit transfer. The target asserts ack64n to
indicate that the target can transfer data using 64 bits. The
ack64n has the same timing as devseln . This signal is not
implemented in pci_mt32 and pci_t32 .
trdyn (1) STS Low Target ready. The trdyn signal is a target output, indicating
that the target can complete the current data transaction. In a
read operation,
trdyn indicates that the target is providing
valid data on the address bus. In a write operation, trdyn
indicates that the target is ready to accept data.
stopn (1) STS Low Stop. The stopn signal is a target device request that indicates
to the bus master to terminate the current transaction. The
stopn signal is used in conjunction with trdyn and devseln
to indicate the type of termination initiated by the target.
perrn STS Low Parity error. The perrn signal indicates a data parity error. The
perrn signal is asserted one clock cycle following the par and
par64 signals or two clock cycles following a data phase with
a parity error. The PCI MegaCore functions assert the perrn
signal if a parity error is detected on the par or par64 signals
and the perrn_ena bit (bit 6) in the command register is set.
The par64 signal is only evaluated during 64-bit transactions
in pci_mt64 and pci_t64 functions. In pci_mt32 and
pci_t32 , only par is evaluated.
serrn Open-Drain Low System error. The serrn signal indicates system error and
address parity error. The PCI MegaCore functions assert
serrn if a parity error is detected during an address phase and
the serrn_ena enable bit (bit 8) in the command register is
set.
Table 3–2. PCI Interface Signals (Part 3 of 4)
Name Type Polarity Description