Altera PCI Compiler User Manual
Page 309
Altera Corporation
User Guide Version 11.1
7–41
October 2011
Functional Description
specifies the ordering rules and behavior of the PCI-Avalon
bridge for the Avalon-to-PCI direction. The entries in this table describe
whether a type in a row may pass a type in a column. The table uses the
following terminology: "No" means a type may not pass another type,
"Yes/No" means a type may pass the other type, but does not have to, and
"Yes" means that a type must pass another type to avoid deadlocks.
Table 7–14. Summary of Ordering in the Avalon-to-PCI Direction
PMW DRR DWR
DRC
DWC
Impl
Spec
Impl
Spec
Impl
Spec
Impl
Spec
Impl
PMW
No
Yes
Yes
Yes
Yes
Yes
Yes
N/A
DRR
No
Yes/ No
Yes/ No
Yes/ No
Yes
Yes/ No
N/A
DWR
No
Yes/ No
Yes
Yes/ No
Yes/ No
Yes
Yes/ No
N/A
DRC
No
Yes
Yes
Yes
No
Yes/ No
Yes/
No
Yes/ No
N/A
DWC
Yes/ No
N/A
Yes
N/A
Yes
N/A
Yes/ No
Yes/ No
N/A
Notes to
(1)
Spec
refers to the PCI Local Bus Specification, Revision 3.0, published by PCI-SIG.
(2)
Impl
refers to the implementation of this passing rule in the PCI-Avalon bridge.
(3)
PMWs, DRRs, and DWRs will not pass other PMWs or DWRs since a request at the head of the Avalon-to-PCI
Command/Write Data buffer will be handled first before any subsequent requests.
(4)
Ordering logic will make sure that PCI-to-Avalon Read Completion data is not indicated as available on the PCI
side until a previous PMW or DWR is issued.
(5)
DWCs are never passed through the PCI-Avalon bridge. The PCI-Avalon bridge can only be the target of a
Configuration Write and these are never delayed.
(6)
DRRs can be held pending in the pending read logic or the Avalon
-to-
PCI Bypassable Read Buffer, allowing them
to be passed by PMWs, DWRs, or DRCs.
(7)
Avalon-MM requires that all read data be returned in the order requested. It is possible they can complete on PCI
in a different order if there are multiple Avalon
-to-
PCI Read Response buffers.
(8)
PMWs cannot pass I/O Writes or Configuration Writes (DWRs). However, since the PCI-Avalon bridge does treat
I/O Writes or Configuration Writes in a non-posted fashion, the deadlock avoidance required by the PCI
specification is not required.
(9)
DRCs cannot pass I/O Writes or Configuration Writes (DWRs). However, since the PCI-Avalon bridge does treat
I/O Writes or Configuration Writes in a non-posted fashion, the deadlock avoidance required by the PCI
specification is not required.
(10) DRCs can be held in the PCI-to-Avalon Read Response buffers, allowing them to be passed by PMWs, DRRs or
DWRs.
(11) If multiple PCI-to-Avalon Read Response buffers are implemented, then one DRC can pass another. Otherwise,
only one delayed read can be in progress at a time.