Altera PCI Compiler - Manual (Page 298)

7–30 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
PCI Master Operation
Figure 7–9 shows the basic data paths and control structures in the
Avalon-to-PCI direction. There is an Avalon-MM slave port that provides
access to the PCI bus.
64 >1 Read Any value Attempt to do a 64 bit burst on PCI ( req64n
asserted). All data phases will have all PCI byte
enables asserted.
Note: If the target address space is only 32-bit
(ack64n not asserted) and the device disconnects
on an odd
DWORD boundary, the transaction is
resumed as a 32-bit burst ( req64n not asserted).
64 >1 Write Any value Attempt to do a 64-bit burst on PCI ( req64n
asserted). All data phases will have PCI byte
enables identical to the Avalon byte enables.
Note: If the target address space is only 32-bit
(ack64n not asserted) and the device disconnects
on an odd
DWORD boundary ( req64n not
asserted), a single cycle 32-bit write operation will
be issued to get back on an even
DWORD
boundary. This is followed by an attempt at a 64-bit
burst that is converted to a 32-bit burst if the device
doesn’t acknowledge 64-bit bursts.
Table 7–9. Translation of Avalon Requests to PCI Requests (Part 2 of 2)
Data
Path
Width
Avalon
Burst
Count
Type of
Operation
Avalon Byte Enables Resulting PCI Operation and Byte Enables