Altera PCI Compiler - Manual (Page 318)

7–50 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Control & Status Registers
Table 7–18 describes the PCI interrupt status register, which shows the
status of all conditions that can cause the assertion of a PCI interrupt.
Table 7–18. PCI Interrupt Status Register – Address: 0x0040 (Part 1 of 2)
Bit Name
Access
Mode
Description
0 ERR_PCI_WRITE_FAILURE RW1C When set to 1 indicates a write to PCI failure (abort or
retry threshold exceeded). This bit can also be cleared
by writing a '1' to the same bit in the Avalon-MM
interrupt status register.
This bit will only be implemented if the bridge is either
operating in the PCI Master/Target Peripheral or PCI
Host-Bridge Device mode.
1 ERR_PCI_READ_FAILURE RW1C When set to 1 indicates a read from PCI failure (abort
or retry threshold exceeded). This bit can also be
cleared by writing a '1' to the same bit in the
Avalon-MM interrupt status register.
This bit will only be implemented if the bridge is either
operating in the PCI Master/Target Peripheral or PCI
Host-Bridge Device mode.
2 ERR_NONP_DATA_DISCARD RW1C When set to 1 indicates non-prefetchable data read
from Avalon-MM was discarded because the PCI read
request was not retried before the discard timer
expired. Note that this bit can also be cleared by a write
of a '1' to the same bit in the Avalon-MM interrupt status
register.
This bit will only be implemented when the
non-prefetchable Avalon-MM master port is
implemented.
6:3 Reserved N/A
7 AV_IRQ_ASSERTED RO Current value of the Avalon-MM interrupt ( IRQ ) input
port to the non-prefetchable Avalon-MM master port
(or prefetchable Avalon-MM master port if the
non-prefetchable port is not used).
0 – Avalon
IRQ is not being signaled.
1 – Avalon IRQ is being signaled.
8 PCI_PERR_REP RO Reflects the current value of PCI status register bit 8,
PERR reported. This bit can only be cleared through a
direct access to the PCI configuration status register.
9 PCI_TABORT_SIG RO Reflects the current value of PCI status register bit 11,
target abort signaled. This bit can only be cleared
through a direct access to the PCI configuration status
register. Because the PCI-Avalon bridge does not
signal target abort, this bit is never set.