Altera PCI Compiler - Manual (Page 216)

4–6 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Testbench Specifications
Testbench
Specifications This section describes the modules used by the PCI testbench including
master commands, setting and controlling target termination responses,
bus parking, and PCI bus speed settings. Refer to
Figure 4–1 for a block
diagram of the PCI testbench. The Altera PCI testbench has the following
modules:
■ Master transactor (mstr_tranx)
■ Target transactor (trgt_tranx)
■ Bus monitor (monitor)
■ Clock generator (clk_gen)
■ Arbiter (arbiter)
■ Pull ups (pull_ups)
■ A local reference design
The PCI testbench consists of VHDL and Verilog HDL. If your application
requires a feature that is not supported by the PCI testbench, you can
modify the source code to add the feature. You can also modify the
existing behavior to fit your application needs.
Table 4–4 shows the PCI bus transactions supported by the PCI testbench.
Table 4–4. PCI Testbench PCI Bus Transaction Support
Transactions Master Transactor Target Transactor Local Master Local Target
Interrupt acknowledge cycle
I/O read v v v v
I/O write v v v v
Memory read v v v v
Memory write v v v v
Configuration read v v
Configuration write v v
Memory read multiple v
Memory write multiple
Dual address cycle
Memory read line v
Memory write and invalidate v