Altera PCI Compiler - Manual (Page 129)

Altera Corporation User Guide Version 11.1 3–55
October 2011
Functional Description
Figure 3–9 shows the same transaction as in Figure 3–8 with the PCI bus
master inserting a wait state. The PCI bus master inserts a wait state by
deasserting irdyn in clock cycle 8. The effect of this wait state on the local
side is shown in clock cycle 9 is that the PCI MegaCore function deasserts
lt_ackn
, and as a result lt_dxfrn is also deasserted. This situation
prevents further data from being transferred on the local side because the
internal pipeline of the PCI MegaCore function is full.
The 64-bit extension signals shown in Figure 3–9 are not applicable to the
pci_mt32 and pci_t32 MegaCore functions.
Figure 3–9. Burst Memory Read Target Transaction with PCI Master Wait State
Note to Figure 3–9 :
(1) This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions.
lt_framen
lt_rdyn
lt_ackn
lt_dxfrn
lt_tsr[11..0] 000 381 000 781 381 781
ad[31..0]
(1) ad[63..32]
cben[3..0]
(1) cben[7..4]
par
(1) par64
framen
(1) req64n
irdyn
devseln
(1) ack64n
trdyn
stopn
l_adro[31..0]
l_cmdo[3..0]
l_adi[31..0]
clk
(1) l_adi[63..32]
Adr
6
Adr-PAR
Z
Adr
6
Z
BE0_L
BE0_H
Z
D0_L
D0_H
D0_L
D0_H
D0-L-PAR
D0-H-PAR
Z
Z
Z
Z
D1_L
D1_H
D2_L
D2_H
D3_L
D3_H
D1_L
D1_H
D2_L
D2_H
D1-L-PAR
D1-H-PAR
D2-L-PAR
D2-H-PAR
2 3 4 5 6 7 9 10 12 8 11 13 1
BE1_L BE2_L
BE1_H BE2_H