Pci-avalon bridge blocks – Altera PCI Compiler User Manual
Page 270
7–2
User Guide Version 11.1
Altera Corporation
PCI Compiler
October 2011
Functional Overview
This section discusses:
■
PCI-Avalon bridge module blocks
■
PCI operational modes
■
Performance profiles
■
OpenCore Plus time-out behavior
PCI-Avalon Bridge Blocks
The PCI-Avalon bridge’s blocks provide a feature-rich foundation that
enables the bridge to manage the connectivity for all three PCI
operational modes:
■
PCI Target-Only Peripheral
■
PCI Master/Target Peripheral
■
PCI Host-Bridge Device
Depending on the operational mode, the PCI-Avalon bridge uses some or
all of the predefined Avalon-MM ports.
shows a generic
PCI-Avalon bridge block diagram, which includes the following blocks:
■
Four predefined Avalon-MM ports
■
Control/status registers
■
PCI master controller (when applicable)
■
PCI target controller
■
PCI bus arbiter (for Master/Target and Host bridge mode)
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Instantiated Altera PCI MegaCore function
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)