Refer to – Altera PCI Compiler User Manual
Page 275
Altera Corporation
User Guide Version 11.1
7–7
October 2011
Functional Description
Figure 7–2. PCI-Avalon Bridge Managing the PCI Target-Only Peripheral Mode, Single-Cycle Transfers Only
shows the block diagram of the PCI-Avalon bridge managing
the connectivity of the PCI Target-Only Peripheral mode with either the
Burst Transfers with Single-Pending Read profile or the Burst Transfers
With Multiple Pending Reads performance profile. The configuration
uses two of the four Avalon-MM ports and has a Host processor and bus
arbiter on the PCI side.
1
Because both the Prefetchable and Non-Prefetchable
Avalon-MM master ports are instantiated, the Avalon bridge
must have at least two memory BARs; one prefetchable memory
BAR and one non-prefetchable memory BAR.
PCI-Avalon Bridge
Target-Only Peripheral Mode
With Single-Cycle Transfers Only
PCI
Target
Controller
PCI
Non-
Prefetchable
Bridge Logic
PCI
MegaCore
Function
System
Interconnect
Fabric
Avalon
Slave
Peripheral
Host
Processor
PCI
Master/
Target
Device
PCI
Bus
Arbiter
PCI
Bus
Non-
Prefetchable
Avalon
Master
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)