Altera PCI Compiler User Manual
Page 226

4–16
User Guide Version 11.1
Altera Corporation
PCI Compiler
October 2011
Local Reference Design
Figure 4–3. Local Reference Design
(1)
The DMA Engine, lm_lastn and local master blocks are not applicable for the pci_t32 and pci_t64 local reference
designs.
shows the memory map of the Altera PCI MegaCore function
required to use the local reference design.
The reference design has the following elements:
■
Local target
■
DMA engine
■
Local master
■
lm_lastn
generator
■
Prefetch
■
LPM RAM
Local
Target
Prefetch
LPM RAM
Altera PCI
MegaCore
Function
Testbench
Modules
Local Reference Design
PCI Bus
dma_sa
dma_bc_la
DMA Engine
(1)
lm_lastn
(1)
Local
Master
(1)
Table 4–8. Memory Map
Memory Region
Mapping
Block size Address Offset
Description
BAR0
Memory Mapped 1 KByte
000-3FF
Maps the LPM_RAM function.
BAR1
I/O Mapped
16 Bytes
0-F
Maps the I/O register.
BAR2
Memory Mapped 1 KByte
000-3FF
Maps the
trg_termination
register and
DMA engine registers. Only the lower 24
Bytes of the address space are used.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)