Altera PCI Compiler - Manual (Page 17)

Altera Corporation User Guide Version 11.1 5
October 2011
About PCI Compiler
■ Hard-coded (fixed) or run-time configurable (dynamic) Avalon-to-
PCI address translation
■ Hard-coded or automatic PCI-to-Avalon address translation
■ Separate Avalon Memory-mapped (Avalon-MM) slave ports for PCI
bus access (PBA) and control register access (CRA)
■ Support for Avalon-MM burst mode
■ Option for independent or common PCI and Avalon clock domains
■ Option to increase PCI read performance by increasing the number
of pending reads and maximum read burst size.
■ Internal Arbiter in Host Bridge and Target/Master mode
General
Description This section provides a general description of the following:
■ PCI MegaCore Functions
■ PCI Testbench
■ PCI Compiler with MegaWizard Plug-in Manager Flow
■ PCI Compiler with SOPC Builder Flow
PCI MegaCore Functions
The PCI MegaCore functions are hardware-tested, high-performance,
flexible implementations of PCI interfaces. These functions handle the
PCI protocol and timing requirements internally. The back-end interface
is designed for easy integration, allowing you to focus your engineering
efforts on value-added custom development to significantly reduce time-
to-market.
Optimized for Altera devices, the PCI MegaCore functions support
configuration, I/O, and memory transactions. The small size of the
functions, combined with the high density of Altera's devices, provides
ample resources for custom local logic to accompany the PCI interface.
The high performance of Altera's devices also enables these functions to
support unlimited cycles of zero wait state memory-burst transactions.
These functions can operate at either 33- or 66-MHz PCI bus clock speeds,
allowing them to achieve up to 132 Megabytes per second (MBytes/s)
throughput in a 32-bit 33-MHz PCI bus system and up to 528 MBytes/s
throughput in a 64-bit 66-MHz PCI bus system.
In the pci_mt64 and pci_mt32 functions, the master and target
interfaces can operate independently, allowing maximum throughput
and efficient usage of the PCI bus. For instance, while the target interface
is accepting zero wait state burst write data, the local logic may
simultaneously request PCI bus mastership, thus minimizing latency.