Altera PCI Compiler - Manual (Page 333)

Altera Corporation User Guide Version 11.1 8–3
October 2011 PCI Compiler
Testbench
PCI Testbench
Files The Altera PCI testbench is included and installed with the PCI Compiler.
Figure 8–2 shows the directory structure of the PCI testbench
subdirectory in the project directory.
1 You will probably modify the PCI testbench directory to
simulate your design, so SOPC Builder will not overwrite the
<core> directory when you regenerate the SOPC Builder system.
To revert back to the default PCI testbench settings at
regeneration time, just delete the pci_sim directory.
Figure 8–2. PCI Testbench Directory Structure
Table 8–1 gives a description of the PCI testbench files provided in the
pci_sim/ <HDL language>/<core> directory. For more information on
these files, refer to “Testbench Specifications” on page 8–4 .
Table 8–1. Files Contained in the pci_sim//
Directory (Part 1 of 2)
File (1) Description
mstr_tranx The master transactor defines the procedures
(VHDL) or tasks (Verilog HDL) that initiate PCI
transactions in the testbench.
mstr_pkg The master package consists of descriptions of
procedures (VHDL) or tasks (Verilog HDL) for master
transactor (mstr_tranx) commands.
trgt_tranx The target transactor simulates the target behavior in
the testbench and responds to PCI transactions.
trgt_tranx_mem_init.dat This file is the memory initialization file for the target
transactor.
monitor This module monitors the PCI transactions on the
bus and reports the results.
arbiter This module contains the PCI bus arbiter.
pull_up This module provides weak pull-up on the tri-stated
signals.
pci_sim
< HDL language>
< core>
Contains PCI testbench files
< project directory>