Altera PCI Compiler User Manual
Page 164

3–90
User Guide Version 11.1
Altera Corporation
PCI Compiler
October 2011
Master Mode Operation
The PCI MegaCore functions support both 64-bit and 32-bit transactions.
The pci_mt64 function supports the following 64-bit PCI memory
transactions:
■
64-bit burst memory read/write
■
64-bit single-cycle memory read/write
1
64-bit single-cycle memory write transactions are only
supported if the Assume ack64n Response option is turned on
in the Parameterize - PCI Compiler wizard. For more
information on the Assume ack64n Response option, refer to
“Assume ack64n Response” on page 2–6
.
Target Local-side Control Signals
lt_abortn
v
v
lt_discn
v
v
lt_rdyn
v
v
lt_framen
v
v
lt_ackn
v
v
lt_dxfrn
v
v
lt_tsr[11..0]
v
v
lirqn
v
v
cache[7..0]
v
v
cmd_reg[5..0]
v
v
stat_reg[5..0]
v
v
Master Local-side Control Signals
lm_req32n
v
v
lm_req64n
v
lm_lastn
v
v
lm_rdyn
v
v
lm_adr_ackn
v
v
lm_ackn
v
v
lm_dxfrn
v
v
lm_tsr[9..0]
v
v
Table 3–37. PCI MegaCore Function Signals (Part 2 of 2)
Signal Name
pci_mt64
pci_mt32
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)