Features, Common features – Altera PCI Compiler User Manual
Page 15

Altera Corporation
User Guide Version 11.1
3
October 2011
About PCI Compiler
shows the level of support offered by the User Guide MegaCore
functions for each Altera device family.
Features
This section summarizes the features of the PCI Compiler.
Common Features
The following list outlines the common features of the PCI Compiler.
■
Fully compliant with the PCI Special Interest Group (PCI SIG)
PCI Local Bus Specification, Revision 3.0
■
Supports both 32-bit and 64-bit interfaces
■
Supports Master/Target and Target-Only modes
Table 2. Device Family Support
Device Family
Support
Arria
®
GX
Final
Arria II GX
Final
Cyclone
®
Final
Cyclone II
Final
Cyclone III
Final
Cyclone III LS
Final
Cyclone IV (E, GX)
Final
HardCopy II
HardCopy Compilation
HardCopy III
Refer to the
page of the Altera website.
HardCopy IV (E, GX)
MAX
®
II
Final
Stratix
®
Final
Stratix GX
Final
Stratix II
Final
Stratix II GX
Final
Stratix III
Final
Stratix
IV (E, GX)
Final
Other device families
No support
Note to
(1)
MAX II devices are supported by the pci_mt32 and pci_t32 MegaCore
functions only.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)