Pci bus commands, Pci target operation, Pci bus commands –15 pci target operation –15 – Altera PCI Compiler User Manual
Page 283
Altera Corporation
User Guide Version 11.1
7–15
October 2011
Functional Description
PCI Bus
Commands
shows the PCI bus commands support for PCI-Avalon bridge.
The bus commands are discussed in greater detail in
and
“PCI Master Operation” on page 7–27
.
PCI Target
Operation
Because it is used with all device types, the PCI target mode is the most
basic operational mode for the PCI-Avalon bridge. In PCI target mode,
the PCI-Avalon bridge supports the following PCI bus transactions:
■
Memory read/write
■
Configuration read/write
■
IO read/write
Table 7–3. PCI Bus Command Support Summary
Command Value
Bus Command Cycle
PCI Target
0b0000
Interrupt acknowledge
No
Ignored
0b0001
Special cycle
No
Ignored
0b0010
I/O read
Yes
Yes
0b0011
I/O write
Yes
Yes
0b0100
Reserved
Ignored
Ignored
0b0101
Reserved
Ignored
Ignored
0b0110
Memory read
Yes
Yes
0b0111
Memory write
Yes
Yes
0b1000
Reserved
Ignored
Ignored
0b1001
Reserved
Ignored
Ignored
0b1010
Configuration read
Yes
Yes
0b1011
Configuration write
Yes
Yes
0b1100
Memory read multiple
Yes
Yes
0b1101
Dual address cycle (DAC)
Yes
0b1110
Memory read line
Yes
Yes
0b1111
Memory write and invalidate
No
Yes
Notes to
:
(1)
Refers to the ability of the PCI-Avalon bridge to initiate a PCI transaction with the indicated command.
(2)
Refers to the ability of the PCI-Avalon bridge to accept a PCI transaction with the indicated command.
(3)
This command is not supported in 32-bit PCI bus width applications.