Altera PCI Compiler User Manual
Pci compiler user guide
PCI Compiler
User Guide
Compiler Version:
11.1
Document Date:
October 2011
c
The PCI Compiler is scheduled for product obsolescence and discontinued support
as describe
. Therefore, Altera does not recommend use of this IP in
new designs. For more information about Altera’s current IP offering, refer to
Altera’s
Table of contents
Document Outline
- PCI Compiler User Guide
- Contents
- About PCI Compiler
- Section I. PCI Compiler With MegaWizard Plug-In Manager Flow
- 1. Getting Started
- 2. Parameter Settings
- 3. Functional Description
- Functional Overview
- PCI Bus Signals
- PCI Bus Commands
- Configuration Registers
- Vendor ID Register
- Device ID Register
- Command Register
- Status Register
- Revision ID Register
- Class Code Register
- Cache Line Size Register
- Latency Timer Register
- Header Type Register
- Base Address Registers
- CardBus CIS Pointer Register
- Subsystem Vendor ID Register
- Subsystem ID Register
- Expansion ROM Base Address Register
- Capabilities Pointer
- Interrupt Line Register
- Interrupt Pin Register
- Minimum Grant Register
- Maximum Latency Register
- Target Mode Operation
- Master Mode Operation
- Host Bridge Operation
- 64-Bit Addressing, Dual Address Cycle (DAC)
- 4. Testbench
- Section II. PCI Compiler With SOPC Builder Flow
- 5. Getting Started
- 6. Parameter Settings
- 7. Functional Description
- 8. Testbench
- Appendix A. Using PCI Constraint File Tcl Scripts
- Additional Information