Altera PCI Compiler - Manual (Page 310)

7–42 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
PCI Master Operation
Ordering PCI-to-Avalon Operations
For requests that hit a prefetchable BAR, ordering is maintained among
the requests by the PCI-to-Avalon command/write data buffer. Both read
and write requests pass through this buffer and are handled in a first-in,
first-out order.
For requests that hit a non-prefetchable BAR, only one of these requests
can be in progress at a time. This request is ordered against any
prefetchable requests by passing the non-prefetchable request valid
indication through the prefetchable PCI-to-Avalon command/write data
buffer.
When a non-prefetchable write request is made valid on the Avalon-MM
side, it must interlock prefetchable write and read requests from being
passed to the Avalon-MM side until the non-prefetchable request has
been accepted by the interconnect. This preserves the ordering of the
non-prefetchable write with respect to prefetchable requests that come
later.
Read response data for Avalon-to-PCI reads must not be allowed to pass
either prefetchable or non-prefetchable writes. To enforce this
requirement, the read response data valid indications are passed from the
PCI bus to the interconnect through both the prefetchable PCI-to-Avalon
command/write data buffer (as sideband data) and the non-prefetchable
command processing logic. The read response data is not made valid
until the prior commands have been passed to the interconnect.
Figure 7–12 shows the ordering logic used in the PCI-to-Avalon direction.
If the prefetchable port is not implemented, the valid indications are
propagated through clock synchronization logic (if needed) instead of the
prefetchable PCI-to-Avalon command/write data buffer (FIFO).