Altera PCI Compiler - Manual (Page 109)

Altera Corporation User Guide Version 11.1 3–35
October 2011
Functional Description
Class Code Register
Class code is a 24-bit read-only register divided into three sub-registers:
base class, sub-class, and programming interface. Refer to the PCI Local
Bus Specification, Revision 3.0 for detailed bit information. The default
value of the class code register is 0xFF0000. You can change the value of
the class_code register using the Parameterize - PCI Compiler wizard.
Refer to
Table 3–19 .
Cache Line Size Register
The cache line size register specifies the system cache line size in DWORDs.
This read/write register is written by system software at power-up. The
value in this register is driven to the local side on the cache[7..0] bus.
The local side must use this value when using the memory read line,
memory read multiple, and memory write and invalidate commands in
master mode. Refer to
Table 3–20 .
1 This register is implemented in the pci_mt64 and pci_mt32
functions only.
Table 3–19. Class Code Register Format
Data Bit Mnemonic Read/Write Definition
23..0 class_code Read Class code
Table 3–20. Cache Line Size Register Format
Data Bit Mnemonic Read/Write Definition
7..0 cache Read/write Cache line size