Altera PCI Compiler User Manual
Page 130
3–56
User Guide Version 11.1
Altera Corporation
PCI Compiler
October 2011
Target Mode Operation
shows the same transaction as shown in
with the
local side inserting a wait state. The local side deasserts lt_rdyn in clock
cycle 6. Deasserting lt_rdyn in clock cycle 6 suspends the local side data
transfer in clock cycle 7 by deasserting the lt_dxfrn signal. Because no
data is transferred in clock cycle 7 from the local side, the PCI MegaCore
function deasserts trdyn in clock cycle 8 thus inserting a PCI wait state.
Figure 3–10. Burst Memory Read Target Transaction with Local-Side Wait State
(1)
This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions.
ad[31..0]
(1) ad[63..32]
cben[3..0]
(1) cben[7..4]
par
(1) par64
framen
(1) req64n
irdyn
devseln
(1) ack64n
trdyn
stopn
l_adro[31..0]
l_cmdo[3..0]
l_adi[31..0]
clk
(1) l_adi[63..32]
Adr
6
Adr-PAR
Z
Adr
6
Z
BE0_L
BE0_H
Z
D0_L
D0_H
D0_L
D0_H
D0-L-PAR
D0-H-PAR
Z
Z
D2_L
D2_H
D3_L
D3_H
D1_L
D1_H
D2_L
D2_H
D1-L-PAR
D1-H-PAR
D2-L-PAR
D2-H-PAR
2
3
4
5
6
7
9
10
12
8
11
13
1
D1_L
D1_H
lt_framen
lt_rdyn
lt_ackn
lt_dxfrn
lt_tsr[11..0]
000
000
381
781
381
781
BE1_L
BE2_L
BE1_H
BE2_H
BE0_H