Altera PCI Compiler - Manual (Page 329)

Altera Corporation User Guide Version 11.1 7–61
October 2011
Functional Description
The Avalon-to-PCI mailbox registers are writable at the addresses shown
in
Table 7–29 . When the Avalon processor writes to one of these registers,
the corresponding bit in the PCI interrupt status register is set to 1.
The PCI-to-Avalon mailbox registers are read only at the addresses
shown in
Table 7–30 . The Avalon processor reads these registers when the
corresponding bit in the Avalon-MM interrupt status register is set to 1.
Table 7–29. Avalon-to-PCI Mailbox Registers – Address Range
0x3A00–0x3A1F
Address Name Access Description
0x3A00 A2P_MAILBOX0 RW Avalon-to-PCI mailbox 0.
0x3A04 A2P_MAILBOX1 RW Avalon-to-PCI mailbox 1.
0x3A08 A2P_MAILBOX2 RW Avalon-to-PCI mailbox 2.
0x3A0C A2P_MAILBOX3 RW Avalon-to-PCI mailbox 3.
0x3A10 A2P_MAILBOX4 RW Avalon-to-PCI mailbox 4.
0x3A14 A2P_MAILBOX5 RW Avalon-to-PCI mailbox 5.
0x3A18 A2P_MAILBOX6 RW Avalon-to-PCI mailbox 6.
0x3A1C A2P_MAILBOX7 RW Avalon-to-PCI mailbox 7.
Table 7–30. PCI-to-Avalon Mailbox Registers – Address Range
0x3B00–0x3B1F
Address Name Access Description
0x3B00 P2A_MAILBOX0 RO PCI-to-Avalon mailbox 0.
0x3B04 P2A_MAILBOX1 RO PCI-to-Avalon mailbox 1.
0x3B08 P2A_MAILBOX2 RO PCI-to-Avalon mailbox 2.
0x3B0C P2A_MAILBOX3 RO PCI-to-Avalon mailbox 3.
0x3B10 P2A_MAILBOX4 RO PCI-to-Avalon mailbox 4.
0x3B14 P2A_MAILBOX5 RO PCI-to-Avalon mailbox 5.
0x3B18 P2A_MAILBOX6 RO PCI-to-Avalon mailbox 6.
0x3B1C P2A_MAILBOX7 RO PCI-to-Avalon mailbox 7.