Altera PCI Compiler - Manual (Page 181)

Altera Corporation User Guide Version 11.1 3–107
October 2011
Functional Description
Figure 3–37. 32-Bit PCI & 64-Bit Local Side Burst Memory Read Master Transaction
I/O & Configuration Read Transactions
I/O and configuration read transactions by definition are 32 bits wide.
The sequence of events is the same as in a 32-bit single-cycle memory read
master transaction, as shown in
Figure 3–36 . This figure applies to both
the pci_mt64 and pci_mt32 MegaCore functions, excluding the 64-bit
extension signals as noted for pci_mt32.
2 3 4 5 6 7 9 10 12
clk
reqn
8 11 1
gntn
ad[31..0]
cben[3..0]
par
framen
req64n
irdyn
devseln
ack64n
trdyn
stopn
Adr
6
Adr-PAR
BE_L
Z
D0_L Z 0
0
Z D1_L D2_L
13
D0-L-PAR D2-L-PAR D1-L-PAR
l_dato[31..0] D0_L D1_L D2_L
l_dato[63..32]
lm_req64n
lm_lastn
lm_adr_ackn
lm_rdyn
lm_tsr[9..0] 000 001 004 002 108 008 000
l_ldat_ackn
l_hdat_ackn
lm_ackn
lm_dxfrn
D3_L
Z
D3-L-PAR
D3_L
l_adi[31..0]
l_cbeni[3..0]
l_cbeni[7..4]
Adr
BE_L
BE_H
6