Figure 3–48, Has t – Altera PCI Compiler User Manual
Page 207

Altera Corporation
User Guide Version 11.1
3–133
October 2011
Functional Description
Figure 3–48. 64-Bit Address, 64-Bit Data Single-Cycle Target Read Transaction
ad[31..0]
ad[63..32]
cben[3..0]
cben[7..4]
par
par64
framen
req64n
irdyn
devseln
ack64n
trdyn
stopn
lt_framen
l_adro[31..0]
l_cmdo[3..0]
lt_ackn
l_adi[31..0]
lt_dxfrn
clk
l_adi[63..32]
l_beno[3..0]
l_beno[7..4]
lt_tsr[11..0]
Adr_L
D
Adr-PAR_L
Z
Adr_L
6
Z
BE0_L
BE0_H
Z
000
983
D0_L
D0_H
D0-L-PAR
BE0_L
BE0_H
000
1
2
3
4
5
6
7
8
9
10
11
D0_L
D0_H
lt_rdyn
D83
Adr_H
Adr_H
6
6
Adr-PAR_H
Z
D0-H-PAR
Adr-PAR_H
l_adro[63..32]
Adr_H
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)