Altera PCI Compiler - Manual (Page 311)

Altera Corporation User Guide Version 11.1 7–43
October 2011
Functional Description
Figure 7–12. Ordering Logic for PCI-to-Avalon Direction
P2A Prefetchable
Command/ Write
Data Buffer (FIFO)
Read/Write Commands
and Write Data to Avalon
Prefetchable Port
To PBA Port
To Avalon
Non-Prefetchable
Port
Command to Avalon
Non-Prefetchable Port
Read Data to
PBA Port
Prefetchable
Read/Write Commands
and Write Data from PCI
A2P Pending
Read Data 0
A2P Pending
Read Data 1
A2P Pending
Read Data N
A2P Non-
Prefetchable
Command Reg
Data
Valid 0
Data
Valid 1
Data
Valid N
Non-
Prefetchable
Cmd
Valid
Data
Valid 0
Data
Valid 1
Data
Valid N
Non-
Prefetchable
Cmd
Valid
From PCI Master
Ctrl
(Non-Prefetchable Cmd Valid for a Write
also prevents Prefetchable commands from
being issued to Avalon or Read Data being
sent to the PBA)
Data from PCI
Non-Prefetchable
Read/Write
Commands from PCI
PBA = PCI Bus Access Avalon Slave Port
A2P = Avalon-to-PCI
P2A = PCI-to-Avalon