Altera PCI Compiler - Manual (Page 256)

6–6 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Value of Multiple Pending Reads
Although up to four pending reads can be issued on the PCI bus, read
data is returned in the order it is issued to the interconnect. This
performance profile provides a significant improvement in PCI read
operations for systems that rely on read operations to transfer data from
PCI devices to Avalon-MM devices.
Value of
Multiple
Pending Reads This section explains the enhanced performance that is possible with
multiple pending read transactions.
Figure 6–1 illustrates the following
burst transfer with multiple pending reads example:
1. PCI Agent 0 requests a read transaction (R0) to address 0x4. The
PCI-Avalon bridge issues a PCI retry, stores the necessary
information from the R0 transaction, and begins to retrieve the
requested data from the PCI-Avalon bridge.
2. Before the R0 transaction completes, PCI Agent 1 requests a read
transaction (R1) to address 0xC. The PCI-Avalon bridge issues
another PCI retry and stores the necessary information to retrieve
the data for R1. Meanwhile, the PCI-Avalon bridge continues to
retrieve the data for R0.
3. At some point the data for R0 is returned, and the PCI-Avalon
bridge immediately begins retrieving the data for R1.
4. PCI Agent 0 issues R0 again, and the PCI-Avalon bridge provides
the requested data and completes R0. Meanwhile, the data for R1 is
returned from the Avalon-MM peripheral.
5. PCI Agent 1 issues R1 again, and the PCI-Avalon bridge provides
the requested data and completes R1.