Altera PCI Compiler User Manual
Page 174

3–100
User Guide Version 11.1
Altera Corporation
PCI Compiler
October 2011
Master Mode Operation
shows the same transaction as in
with the local
side inserting a wait state. This figure applies to both the pci_mt64 and
pci_mt32
MegaCore functions, excluding the 64-bit extension signals as
noted for pci_mt32.
Figure 3–33. Burst Memory Read Master Transaction with Local-Side Wait State
Notes to
:
(1)
This signal is not applicable to the pci_mt32 MegaCore function.
(2)
For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions.
2
3
4
5
6
7
9
10
12
clk
reqn
8
11
1
gntn
ad[31..0]
(1) ad[63..32]
cben[3..0]
(1) cben[7..4]
par
(1) par64
framen
(1) req64n
irdyn
devseln
(1) ack64n
trdyn
stopn
Adr
6
Adr-PAR
BE_L
Z
D0_L
D0_H
D0-H-PAR
Z
0
0
0
0
Z
Z
BE_H
Z
D1_L
D2_L
D1_H
D2_H
13
Z
Z
Z
D2-H-PAR
D1-H-PAR
D0-L-PAR
D1-L-PAR
D2-L-PAR
l_dato[31..0]
(1), (2) lm_req64n
lm_lastn
lm_adr_ackn
lm_rdyn
lm_tsr[9..0]
000
001
004
002
308
308
008
208
000
(1) l_ldat_ackn
(1) l_hdat_ackn
lm_ackn
lm_dxfrn
208
D0_L
D1_L
D2_L
D0_H D1_H
D2_H
(1) l_dato[63..32]
200
14
l_adi[31..0]
Adr
l_cbeni[3..0]
(1) l_cbeni[7..4]
6
BE_L
BE_H
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
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- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
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- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
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- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
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- IP Compiler for PCI Express (372 pages)
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- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)