Complete the connections in sopc builder – Altera PCI Compiler User Manual
Page 242
5–8
User Guide Version 11.1
Altera Corporation
PCI Compiler
October 2011
PCI Compiler with SOPC Builder Flow Design Walkthrough
Complete the Connections in SOPC Builder
You need to connect the ports of the components in your SOPC system.
1.
Move the pointer over the Connections column. Potential
connections are displayed.
2.
Connect the following master-slave ports:
shows the complete connections.
Figure 5–2. Master-Slave Port Connections
3.
Under Clock Settings, double-click the default speed (MHz) for
clk_0
and type 100.
Table 5–1. Master-Slave Port Connections
Master Port
Slave Port
pci_compiler
bar0_Prefetchable
onchip_mem
s1
pci_compiler
bar1_Prefetchable
pci_compiler
Control_Register_Access
pci_compiler
bar1_Prefetchable
dma
control_port_slave
dma
read_master
onchip_mem
s1
dma
read_master
pci_compiler
PCI_Bus_Access
dma
write_master
onchip_mem
s1
dma
write_master
pci_compiler
PCI_Bus_Access
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)