Altera PCI Compiler - Manual (Page 290)

7–22 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
PCI Target Operation
These features result in higher bandwidth, but introduce higher latency
and require more resources.
Prefetchable Write Operations
When PCI write requests that hit prefetchable BARs are claimed from the
PCI bus, they are passed to the interconnect as write requests. Both PCI
memory write and PCI memory write and invalidate commands are
treated identically inside the prefetchable PCI-Avalon bridge logic.
When a PCI memory write is claimed from the PCI interface, the BAR hit
information, BAR offset address, and initial data are written to the
PCI-to-Avalon command/write data buffer. Memory write transfers are
broken into 32-byte boundaries before they are issued on the
interconnect. The memory write command is committed to the buffer
when either the PCI write command ends on the PCI interface or the burst
data reaches a 32-byte boundary. Once the command is committed to the
buffer, it becomes visible to the Avalon-MM side of the buffer and the
Avalon-MM write operation can begin. Therefore, long PCI memory
burst write transactions are broken into 32-byte Avalon-MM transfers.
However, depending on the PCI address, the first and/or last resulting
Avalon-MM write transaction can be less than 32-bytes. The PCI-Avalon
bridge calculates the appropriate Avalon-MM address for all transfers.
If the incoming PCI write specifies the "cacheline wrap dode" burst order,
the request is target disconnected on the first data phase. The single data
phase worth of write data is committed to the PCI-to-Avalon
command/write data buffer.
For all data phases of PCI-to-Avalon write requests, the PCI byte enables
are passed through to the Avalon-MM byte enables unchanged.
PCI write bursts can be terminated for a number of reasons. The reasons
and resulting actions by the PCI target controller are enumerated in
Table 7–6 .
Table 7–6. Termination of PCI Writes That Hit a Prefetchable BAR as a PCI Target (Part 1 of 2)
Termination Condition Resulting Action
Normal master-initiated termination The current transaction is committed to the
PCI-to-Avalon command/write data buffer at its current
length.
Some bytes are disabled in the current data phase The transaction will continue and the byte enables will
be passed along to Avalon-MM unchanged.