Altera PCI Compiler - Manual (Page 326)

7–58 User Guide Version 11.1 Altera Corporation
PCI Compiler October 2011
Control & Status Registers
7 INTAN_RISE RW1C This bit is set to 1 when the PCI intan signal changes
from 0 to 1. This bit is set to 0 when a '1' is written to it and
intan does not transition in the same cycle as the write.
This bit is only implemented when the bridge is operating
in the PCI Host-Bridge Device mode.
8 PCI_PERR_REP RO Reflects the current value of PCI status register bit 8, PERR
reported. This bit can only be cleared through a direct
access to the PCI configuration status register.
9 PCI_TABORT_SIG RO Reflects the current value of PCI configuration status
register bit 11, target abort signaled. This bit can only be
cleared through a direct access to the PCI configuration
status register.
10 PCI_TABORT_RCVD RO Reflects the current value of PCI configuration status
register bit 12, target abort received. This bit can only be
cleared through a direct access to the PCI configuration
status register.
11 PCI_MABORT_RCVD RO Reflects the current value of the PCI configuration status
register bit 13, master abort received. This bit can only be
cleared through a direct access to the PCI configuration
status register.
12 PCI_SERR_SIG RO Reflects the current value of PCI configuration status
register bit 14, system error signaled. This bit can only be
cleared through a direct access to the PCI configuration
status register
13 PCI_PERR_DET RO Reflects the current value of PCI configuration status
register bit 15,
PERR detected.
14:15 Reserved N/A
16 P2A_MAILBOX_INT0 RW1C Set to 1 when the P2A_MAILBOX0 register is written to.
17 P2A_MAILBOX_INT1 RW1C Set to 1 when the P2A_MAILBOX1 register is written to.
18 P2A_MAILBOX_INT2 RW1C Set to 1 when the P2A_MAILBOX2 register is written to.
19 P2A_MAILBOX_INT3 RW1C Set to 1 when the P2A_MAILBOX3 register is written to.
20 P2A_MAILBOX_INT4 RW1C Set to 1 when the P2A_MAILBOX4 register is written to.
21 P2A_MAILBOX_INT5 RW1C Set to 1 when the P2A_MAILBOX5 register is written to.
22 P2A_MAILBOX_INT6 RW1C Set to 1 when the P2A_MAILBOX6 register is written to.
23 P2A_MAILBOX_INT7 RW1C Set to 1 when the P2A_MAILBOX7 register is written to.
31:24 Reserved N/A
Table 7–26. Avalon Interrupt Status Register – Address 0x3060 (Part 2 of 2)
Bit Name
Access
Mode
Description