Altera PCI Compiler - Manual (Page 7)

Altera Corporation User Guide Version 11.1 vii
PCI Compiler
Contents
Interrupt Pin Register .................................................................................................................... 3–43
Minimum Grant Register .............................................................................................................. 3–43
Maximum Latency Register .......................................................................................................... 3–44
Target Mode Operation ...................................................................................................................... 3–44
Target Read Transactions .............................................................................................................. 3–48
Memory Read Transactions ..................................................................................................... 3–48
I/O Read Transactions ............................................................................................................. 3–61
Configuration Read Transactions ........................................................................................... 3–62
Target Write Transactions ............................................................................................................. 3–63
Memory Write Transactions .................................................................................................... 3–63
I/O Write Transactions ............................................................................................................ 3–75
Configuration Write Transactions .......................................................................................... 3–76
Target Transaction Terminations ................................................................................................. 3–77
Retry ............................................................................................................................................ 3–77
Disconnect .................................................................................................................................. 3–79
Target Abort ............................................................................................................................... 3–86
Additional Design Guidelines for Target Transactions ............................................................ 3–88
Master Mode Operation ..................................................................................................................... 3–88
PCI Bus Parking .............................................................................................................................. 3–92
Design Consideration ............................................................................................................... 3–92
Master Read Transactions ............................................................................................................. 3–93
Memory Read Transactions ..................................................................................................... 3–93
I/O & Configuration Read Transactions ............................................................................. 3–107
Master Write Transactions .......................................................................................................... 3–108
Memory Write Transactions .................................................................................................. 3–108
I/O & Configuration Write Master Transactions ............................................................... 3–124
Abnormal Master Transaction Termination ............................................................................. 3–125
Latency Timer Expires ............................................................................................................ 3–125
Retry .......................................................................................................................................... 3–125
Disconnect Without Data ....................................................................................................... 3–126
Disconnect with Data ............................................................................................................. 3–126
Target Abort ............................................................................................................................. 3–126
Master Abort ............................................................................................................................ 3–126
Host Bridge Operation ...................................................................................................................... 3–127
Using the PCI MegaCore Function as a Host Bridge .............................................................. 3–127
PCI Configuration Read Transaction from the pci_mt64 Local Master Device to the Internal
Configuration Space ............................................................................................................... 3–127
PCI Configuration Write Transaction from the pci_mt64 Local Master Device to the Internal
Configuration Space ............................................................................................................... 3–129
64-Bit Addressing, Dual Address Cycle (DAC) ............................................................................ 3–131
Target Mode Operation ............................................................................................................... 3–131
64-Bit Address, 64-Bit Data Single-Cycle Target Read Transaction ................................ 3–132
Master Mode Operation .............................................................................................................. 3–134
64-Bit Address, 64-Bit Data Master Burst Memory Read Transaction ............................ 3–134
Chapter 4. Testbench
General Description ............................................................................................................................... 4–1