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Configuring msg block message timeout -17, Configuring msg block message timeout – Rockwell Automation DAG6.5.8 APPLICATION GUIDE SCADA SYSTEM User Manual

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Publication AG-UM008C-EN-P - February 2005

Configuring MicroLogix 1000 Controllers 6-17

The MicroLogix 1000 controller uses word addressing, while the
PLC-5 processor uses byte addressing. In the Targets CIF Offset
field of the MicroLogix 1000 MSG control block, enter a word
value equivalent to the byte (element) of the PLC-5 file number
you want to write data into or read data from. For example in
Figure 6.5, the Targets CIF Offset is 20; this corresponds to
element 10

10

in a PLC-5 processor because one word

=

two

bytes. Never enter an odd value for a Targets CIF Offset.

The MicroLogix 1000 controller can only directly address words

0

10

-127

10

in a PLC-5 data table file. By specifying a byte-offset of

254 in the Targets CIF Offset field and specifying a Message
Length of 41, you can indirectly address words 128

10

-167

10

in a

PLC-5 data table file. The maximum read or write message
length for a MicroLogix 1000 controller is 41 elements.

In the PLC-5 processor, create integer files that correspond to the
station addresses of the MicroLogix 1000 controllers that will be
sending messages to the PLC-5 processor. Because, when a
MicroLogix 1000 sends a MSG instruction to a PLC-5 processor,
the MicroLogix 1000 controller reads data from and writes data
to a PLC-5 integer file that is equal to the MicroLogix 1000
controller’s DF1 station address.

Keep the following considerations in mind when configuring
messages between a MicroLogix 1000 controller and another
MicroLogix, SLC 500 or Logix controller:

Use the 500CPU type MSG instruction. The maximum read or
write message length is 41 elements.

In a Logix controller, a controller-scoped tagname must be
mapped to a PLC 3, 5/SLC file number.

Configuring MSG Block Message Timeout

The MicroLogix 1000 does not have a message timeout built into the
MSG instruction. So the user should assign a timer with the
appropriate MSG timeout bit control for each MSG instruction. See
Figure 6.4 for a sample of MSG Timeout ladder logic.