Rainbow Electronics W90P710CDG User Manual
Page 88
W90P710CD/W90P710CDG
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Instruction Cache Load and Lock
The W90P710 supports a cache-locking feature that can be used to lock critical sections of code into I-
Cache to guarantee quick access. Lockdown can be performed with a granularity of one cache line. The
smallest space, which can be locked down, is 4 words. After a line is locked, it operates as a regular
instruction SRAM. Lines locked are not replaced during misses and not affected by flush per line
command.
To load and lock instruction, the following sequence should be followed:
1.
Write the start address of the instructions to be locked into CAHADR register.
2. Set
LDLK and ICAH bits in the CAHCON register.
3.
Increased the address by 16 and written into CAHADR register.
4. Set
LDLK and ICAH bits in the CAHCON register.
5.
Repeat the steps 3 and 4, until the desired instructions are all locked.
When using I-Cache load and lock command, there are some notes should be cared.
y
The programs executing load and lock operation should be held in a non-cacheable area of
memory.
y
The cache should be enabled and interrupts should be disabled.
y
Software must flush the cache before execute load and lock to ensure that the code to be locked
down is not already in the cache.
Instruction Cache Unlock
The unlock operation is used to unlock previously locked cache lines. After unlock, the “L” bit of the line
is cleared to “0”. W90P710 has two unlock command, unlock line and unlock all.
The unlock line operation is performed on a cache line granularity. In case the line is found in the cache,
it is unlocked and starts to operate as a regular valid cache line. In case the line is not found in the
cache, no operation is done and the command terminates with no exception. To unlock one line the
following unlock line sequence should be followed:
1.
Write the address of the line to be unlocked into the CAHADR Register.
2. Set
the
ULKS and ICAH bits in the CAHCON register.
The unlock all operation is used to unlock the whole I-Cache. This operation is performed on all cache
lines. In case a line is locked, it is unlocked and starts to operate as regular valid cache line. In case a
line is not locked or if it is invalid, no operation is performed. To unlock the whole cache, set the ULKA
and ICAH bits.