Rainbow Electronics W90P710CDG User Manual

Page 317

W90P710CD/W90P710CDG

Publication Release Date: September 19, 2006

- 317 -

Revision B2

BITS

DESCRIPTIONS

[31:3] Reserved -

[2] R_FIFO_FULL

Record FIFO full indicator bit
R_FIFO_FULL=0, the record FIFO not full
R_FIFO_FULL=1, the record FIFO is full
The R_FIFO_READY bit is read only

[1] R_DMA_END_IRQ

DMA end address interrupt request bit for record
R_DMA_END_IRQ=0, means record DMA address does not
reach the end address
R_DMA_END_IRQ=1, means record DMA address reach the end
address
The R_DMA_END_IRQ bit is readable, and only can be clear by
write “1” to this bit

[0]

R_DMA_MIDDLE

_IRQ

DMA address interrupt request bit for record
R_DMA_MIDDLE_IRQ=0, means record DMA address does not
reach the middle address
R_DMA_MIDDLE_IRQ=1, means record DMA address reach the

middle address

The R_DMA_MIDDLE_IRQ bit is readable, and only can be clear
by write “1” to this bit

DMA play destination base address (ACTL_PDSTB)

REGISTER

ADDRESS

R/W

DESCRIPTION

RESET VALUE

ACTL_PDSTB 0xFFF0_9018 R/W

DMA play destination base address

0x0000_0000

The value in ACTL_PDSTB register is the play destination base address of DMA, and only could be
changed by CPU.

Reserved

R_FIFO_FULL

R_DMA_END_IRQ R_DMA_MIDDLE_IRQ