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Rainbow Electronics W90P710CDG User Manual

Page 150

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W90P710CD/W90P710CDG

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BITS

DESCRIPTIONS

[31:16] Reserved

[15:0] MREPC

The MAC Remote Pause Count shows the current value of the
down count timer that starts to count down from the value of operand
of the transmitted PAUSE control frame.

DMA Receive Frame Status Register (DMARFS)

The DMARFS is used to keep the Length/Type field of each incoming Ethernet packet. This register is
writing clear and writes 1 to corresponding bit clears the bit.

REGISTER

ADDRESS

R/W

DESCRIPTION

RESET VALUE

DMARFS 0xFFF0_30C8 R/W

DMA

Receive Frame Status Register

0x0000_0000

31

30

29

28

27

26

25

24

Reserved

23

22

21

20

19

18

17

16

Reserved

15

14

13

12

11

10

9

8

RXFLT

7

6

5

4

3

2

1

0

RXFLT

BITS

DESCRIPTIONS

[31:16] Reserved

[15:0] RXFLT

The Receive Frame Length/Type keeps the Length/Type field of
each incoming Ethernet packet. If the bit EnDEN of MIEN is enabled
and the Length/Type field of incoming packet has received, the bit
DENI of MISTA will be set and trigger interrupt. And, the content of
Length/Type field will be stored in RXFLT.