Rainbow Electronics W90P710CDG - Manual (Page 85)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 85 - Revision B2
Continued.
BITS DESCRIPTION
[3:0] MCLK_O_D
MCLK output delay adjustment
MCLK_O_D [3:0] Gate
Delay
MCLK_O_D [3:0] Gate
Delay
0 0 0 0 P-0 1 0 0 0 N-0
0 0 0 1 P-1 1 0 0 1 N-1
0 0 1 0 P-2 1 0 1 0 N-2
0 0 1 1 P-3 1 0 1 1 N-3
0 1 0 0 P-4 1 1 0 0 N-4
0 1 0 1 P-5 1 1 0 1 N-5
0 1 1 0 P-6 1 1 1 0 N-6
0 1 1 1 P-7 1 1 1 1 N-7
NOTE: “P-x” means MCLKO shift “X” gates delay by refer HCLK
positive edge, “N-x” means MCLKO shift “X” gates delay by refer HCLK
negative edge. MCLK is the output pin of MCLKO, which is an internal
signal on chip.